The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a method for manufacturing the same, which reduces parasitic capacitance of a bit line when forming a cell array contained in a high-integration semiconductor memory device.
Semiconductor devices are formed by implanting impurities or depositing a new material at a predetermined region in a silicon wafer. A representative example of the semiconductor devices may be a semiconductor memory device. The semiconductor memory device includes a large number of elements, for example, transistors, capacitors, resistors, and the like. Individual elements are interconnected through a conductive layer so that data or signals are communicated therebetween.
With the increasing development in technologies for manufacturing semiconductor devices, many people are conducting intensive research into a method for forming many more chips on one wafer by increasing the degree of integration of semiconductor devices. In order to increase the degree of integration, a minimum line width required for the design rules is made smaller. In addition, there is a need for semiconductor devices to be operated at a higher speed and reduced power consumption.
In order to increase the degree of integration of a semiconductor device, the size of each constituent element contained in the semiconductor device should be reduced and the length and width of connection wires should also be reduced. A representative example of the wiring used for a semiconductor memory device may be a word line for transferring a control signal or a bit line for transferring data. When reducing the cross-section of the word line or the bit line, resistance increases. The increase in resistance deteriorates a data transfer rate, increases the amount of power consumption, and finally results in a reduction in operational stability of the semiconductor memory device.
On the other hand, if the cross-sectional size of a word line or bit line is maintained as in the related art, when the degree of integration increases, a physical distance between a word line and a bit line is unavoidably reduced. This increases the parasitic capacitance. Compared with the bit line, the word line, used for transferring a control signal, has a relatively high potential. The bit line, used for transferring data received from a unit cell capacitor, may not operate normally due to the increase in parasitic capacitance and the high potential of the word line. If data is not smoothly and normally transferred through the bit line, a sense amplifier used to detect and amplify data may not detect the data. This results in a reading error.
In order to solve the problems caused by the increase of parasitic capacitance of the bit line, a method for increasing the amount of electric charges contained in the unit cell of a semiconductor memory device may be used. However, in order to implement the aforementioned method, a capacitor contained in the unit cell of the semiconductor memory device should be increased in size. However, the higher the degree of integration, the smaller the region occupied by the capacitor contained in the semiconductor memory device. That is, there is a limitation in increasing the size of a capacitor contained in the unit cell while increasing the degree of integration of the semiconductor memory device.
FIGS. 1a to 1c are conceptual diagrams illustrating cell regions and problems of with a conventional semiconductor memory device. FIG. 1a, 1b, or 1c illustrates a 6F2-sized unit cell contained in a semiconductor memory device. FIG. 1a illustrates a semiconductor memory device that includes a recess gate in a cell region. FIGS. 1b to 1c illustrate a semiconductor memory device including a buried gate in a cell region. In the meantime, a conventional gate pattern a planar channel region is formed in a peripheral region of the conventional semiconductor memory device illustrated in FIGS. 1a to 1c. 
Referring to FIG. 1a, a cell region of the semiconductor memory device includes a gate pattern 110 in an active region 102, wherein the gate pattern 110 includes a lower gate electrode 112, an upper gate electrode 114, a gate hard mask layer 116, and a gate spacer 118. After forming a recess in the cell region, a conductive material is deposited on both the cell region and the peripheral region, so that the gate pattern 110 of the cell region and another gate pattern 110′ of the peripheral region are simultaneously formed.
An insulation layer 165 formed on the active region 102 is etched at both sides of the gate pattern 110, so that a contact plug 106 is formed. In this case, the contact plug 106 is connected to a storage node contact 122 connected to a capacitor (not shown) and a bit line contact plug 124 connected to a bit line 126. A bit-line hard mask layer 128 is formed on the bit line 126. The storage node contact 122, the bit line 126, and the bit line contact plug 124 are electrically insulated by an insulation layer (not shown).
Referring to a structure of the cell region illustrated in FIG. 1a, although the above electrical insulation is implemented with the insulation layer, parasitic capacitance occurs in an overlapping region between the bit line 126 and the storage node contact 122. In addition, parasitic capacitance may also occur between the contact plug 106 connected to the bit line contact plug 124 and the gate pattern 110. In other words, as can be seen from the cell region illustrated in FIG. 1a, electric charges having different characteristics may be transferred to or be stored in a neighboring conductive region. The higher the degree of integration of the semiconductor memory device, the shorter a physical distance between neighboring conductive regions, resulting in the increase of parasitic capacitance. In order to solve this problem, a semiconductor device, including a buried gate, has been recently proposed. In the buried gate, the top of the gate pattern is formed below the surface of the active region.
Referring to FIG. 1b, a semiconductor memory device includes a gate pattern 150 composed of a gate electrode 152 and a gate hard mask layer 156 in an active region 142. In this case, since one gate pattern of the cell region and another gate pattern of the peripheral region are different in structure and height, an insulation layer is etched by a cell open mask or a cell close mask (i.e., a mask that covers the entire peripheral region and open to the entire cell region and vice versa), so that one gate pattern 110 of the cell region and the other gate pattern 110′ of the peripheral region are formed.
Since the gate pattern 150 is buried in the active region, the contact plug 106 formed on the active region 142 illustrated in FIG. 1a is not required for the semiconductor memory device in FIG. 1b. However, the storage node contact 162, the bit line 166, and the bit line contact plug 164 are electrically insulated by the insulation layer 165. Also, the storage node contact 162 and the bit line contact plug 164 are formed after the gate pattern 110′ of the peripheral region is formed in the same manner as in FIG. 1a. The insulation layer 165 is deposited in the cell region before the gate pattern 110′ of the peripheral region is formed, so that the gate pattern 150 located under the insulation layer 165 is protected. In the cell region before the gate pattern 110′ of the peripheral region is formed, the insulation layer 165 is etched so that an upper part of the active region 142 is exposed. The storage node contact 162 and the bit line contact plug 163 are directly connected to an upper part of the exposed active region 142. The bit line 166 and the bit line hard mask layer 168 are formed on the bit line contact plug 164.
The contact plug is not required for the semiconductor memory device illustrated in FIG. 1b, so that parasitic capacitance causing the problem in FIG. 1a is not generated in FIG. 1b. However, since a thickness of the insulation 165 is not reduced, it is difficult to secure a process margin for forming the storage node contact 162 and the bit line contact plug 164.
In more detail, the insulation layer 165 is deposited with a large thickness and then etched to expose the surface of an upper part of the active region 142. Finally, a conductive material is filled into the recess so that the storage node contact 162 and the bit line contact plug 164 are formed. However, it is difficult to expose the surface of an upper part of the active region 142 by etching the thickly-deposited insulation layer due to the reduction in the design rules. If a conductive material is filled into a recess where the active region 142 is not completely exposed, junction resistance increases among the storage node contact 162, the bit line contact plug 164, and a source/drain region contained in the active region 142. This may cause a malfunction to occur in the semiconductor memory device. Due to this problem, it is difficult to form each of the storage node contacts 162 and the bit line contact plug 164 to a sufficient depth to reduce the parasitic capacitance.
Referring to FIG. 1c, a semiconductor memory device includes a gate pattern 180 in an active region 172, where the gate pattern 180 includes a gate electrode 182 and a hard mask layer 186. Although the semiconductor memory device of FIG. 1c is similar to that of FIG. 1b in light of the presence of a buried gate structure, the insulation layer 165 is removed to form a storage node contact 192 and a bit line contact plug 194 so that the distance between a bit line 196 and the active region 172 is reduced. A pad nitride layer (not shown) is formed between the bit line 196 and the active region 172. Particularly, the insulation layer is completely etched using a cell open mask or a cell close mask, so that the gate pattern 180 of the cell region and the gate pattern 110′ of the peripheral region are formed.
In more detail, if the bit line contact plug 194 connected to the active region 172 of the cell region and the bit line 196 are simultaneously formed using the same material as that of a gate electrode of the gate pattern formed in the peripheral region, each of the bit line contact plug 194, the bit line 196, and the bit line hard mask layer 198 may be formed to have the same or less height than the gate pattern of FIG. 1a. Through the above-mentioned processes, the height for forming the bit line 196 is reduced, so that the semiconductor memory device of FIG. 1c has no difficulty in forming the storage node contact 192 and the bit line contact plug 194, differently from the semiconductor memory device of FIG. 1b. 
A semiconductor memory device illustrated in FIG. 1c has an advantage in that a storage node contact 192 and a bit line contact plug 194 can be easily formed, however, parasitic capacitance unavoidably increases in the same manner as in FIG. 1a. The reason why the parasitic capacitance increases is that a neighboring region among the bit line contact plug 194, the bit line 196, and the storage node contact 192 becomes larger, and the distance between the bit line contact plug 194 and the gate pattern 180 becomes shorter.
As described above, the higher the degree of integration of the semiconductor memory device, the higher the parasitic capacitance. In the meantime, a unit cell structure for restricting the occurrence of parasitic capacitance does not have a sufficient process margin for forming the storage node contact or the bit line contact plug, so that the possibility of generating an unexpected defective part in the unit cell structure increases.